Conventional content addressable memories (CAMs) can provide rapid matching between a specific pattern of received data bits, commonly known as a search key or comparand, and data values stored in a content addressable memory (CAM) array. In a CAM device, a CAM array can be searched in parallel. If a match occurs between each bit of a stored data value and a corresponding bit of an applied comparand, a match indication can be generated, via a match line, to indicate that the applied comparand is stored in the CAM. Data associated with the matching CAM location can then be returned. Thus, in a CAM device, a result can be determined from finding a matching value (content), and not from an address for a value, as is typically done for a random access memory (RAM).
Conventional CAMs are typically composed of a number of CAM cells that can be arranged into an array. Conventional CAM cells can include binary CAM cells as well as ternary CAM cells.
A conventional binary CAM cell can store a data bit value (i.e., logic “0” or logic “1”). When such a stored data bit value matches an applied compare data bit value, the binary CAM cell can maintain a high impedance between a precharged match line and a lower discharge potential. If all binary CAM cells connected to a given match line provide a match result, the match line can maintain the precharged state, indicating a match result. When a stored data bit value does not match an applied compare data bit value, the binary CAM cell can provide a low impedance between a precharged match line and lower discharge potential. Thus, if any one of the binary CAM cells connected to a given match line provides a no match result, the match line will be discharged, indicating a no match (miss) result for the comparand.
A conventional ternary (TCAM) cell can store three states, including a logic “0”, logic “1” and a “don't care”. When such a TCAM cell stores a logic “0” or logic “1”, the TCAM cell can provide the same essential match operation as a binary CAM cell. However, when such a TCAM cell stores a “don't care” value, the TCAM cell can provide a match result regardless of the compare data value applied to the TCAM cell.
A schematic diagram of a conventional “X/Y” type TCAM cell is shown in FIG. 9. Referring to FIG. 9, a conventional TCAM cell 900 can generally include a “stack” 902 and two static random access memory (SRAM) cells 904-0 and 9041. In the particular arrangement of FIG. 9, SRAM cells (904-0 and 904-1) can store data bits (referred to typically as an X-value and Y-value) to be compared by transistors within stack 902 against externally supplied comparand data provided at inputs CD and BCD. An input CD can provide a compare data value, while input BCD can provide a complementary compare data value (compare data “bar”). That is CD and BCD are complementary values with respect to each other. The stack 902 of FIG. 9 includes four N-type metal-oxide-semiconductor (MOS) transistors.
As noted above, FIG. 9 shows an “X/Y” type TCAM cell. In such an arrangement, a masking value (don't care) is determined according to a data value stored in both SRAM cells (904-0 and 9041). This is in contrast to a “V/M” type TCAM cell in which a masking value is determined according to one data value (e.g., M) stored in a single SRAM cell.
Conventional TCAM cells like that of FIG. 9 and CAM devices employing such CAM cells, can have limitations, however. In particular, in many cases write operations to SRAM cells within a same TCAM cell are not separable. That is, data may not be written to one SRAM cell without accessing the other in the same operation. One way of referring to this limitation is to call write operations “atomic” (i.e., not being capable of being split between storage elements). It follows that a “non-atomic” write operation would be capable of writing data to just one SRAM cell of a CAM cell, if possible.
In addition, conventional approaches typically require write operations to occur on a row-by-row basis. That is, it is typically not possible to write data in a column wise fashion in a CAM array to multiple rows. One way of referring to this limitation is to note that conventional write operations are not column wise bit-maskable.
A second conventional TCAM cell is shown in FIG. 10, and designated by the general reference character 1000. The arrangement of FIG. 10 can include some of the same structures as that of FIG. 9. However, CAM cell 1000 can include additional bit lines BB1/BB2 (1050-0 and 1050-1) that can enable both bit-maskable and non-atomic write operations. In particular, complementary write data can be driven on bit line pairs B1/BB1 and/or B2/BB2 to write data to either SRAM cell (1004-0 or 1004-1).
However the inclusion of such bit lines can result in a significantly larger CAM cell size. Potentially, a size of CAM cell 1000 can be as much as 50% greater than that of FIG. 9.